Usage guides# Adding Your Designs Regression & Exploration Overview Default Test Set Results Usage Output Command line arguments Hardening Macros Configuration Variables Synthesis Static Timing Analysis Floorplan IO Placement Placement Global Placement Optimizations Resizer optimizations Detailed Placement Clock Tree Synthesis Power Grid/Power Distribution Network Diode Insertion Routing GDS Streaming Final Reports and Checks Chip Level Integration The Current Methodology Hardening Macros Hardening The Core Hardening The Full Chip Power_routing Macros Core General Notes Power Grid/Power Distribution Network Chip Level Core Level Macro Level Custom-Building PDKs