Additional Material#

There are some cool tutorials and guides on using OpenLane to harden chips. Though do note, guides, especially video tutorials and webinars, tend to become out of date.

Additionally, we are also going to link to academic publications about OpenLane if you are interested in reading and/or citing it.

Text Guides#

Official#

Community#

English#

日本語#

Español#

Videos#

Publications#

This is a list of publications about OpenLane, sorted from newest to oldest.

  • R. Timothy Edwards, M. Shalan and M. Kassem, “Real Silicon using Open Source EDA,” in IEEE Design & Test, doi: 10.1109/MDAT.2021.3050000. Paper

  • M. Shalan and T. Edwards, “Building OpenLANE: A 130nm OpenROAD-based Tapeout-Proven Flow: Invited Paper,” 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-6. Paper

  • Ahmed Ghazy and Mohamed Shalan, “OpenLANE: The Open-Source Digital ASIC Implementation Flow”, Article No.21, Workshop on Open-Source EDA Technology (WOSET), 2020. Paper