The OpenLane Documentation¶
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. It also provides a number of custom scripts for design exploration and optimization.
The flow performs all ASIC implementation steps from RTL all the way down to GDSII. Currently, it supports both A and B variants of the sky130 PDK, the C variant of the gf180mcu PDK, and instructions to add support for other (including proprietary) PDKs are documented.
OpenLane abstracts the underlying open source utilities, and allows users to configure all their behavior with just a single configuration file.
Check the sidebar to the left to get started.
- Getting Started
- Installation
- Ubuntu 20.04+
- macOS 11+
- Windows 10+
- Other Linux
- Installation steps
- Installation of Required Packages
- Docker Installation
- Making Docker available without root (Linux)
- Checking the Docker Installation
- Troubleshooting docker installation issues [Linux/Ubuntu only]
- Checking Installation Requirements
- Download and Install OpenLane
- Optional: Viewing Test Design Outputs
- Updating OpenLane
- Quick-Start Guide
- Installation
- OpenLane Architecture
- Usage guides
- Tutorials
- Hierarchical chip design (with macros)
- Designing a chip with an OpenRAM (sky130)
- Reference Manual
- Command-Line Arguments
- Design Configuration Files
- Flow Configuration Variables
- General
- Linting
- Synthesis
- Static Timing Analysis (STA)
- Floorplanning (FP)
- All Resizer (RSZ) Steps
- Global and Detailed Placement (GPL/DPL)
- Clock Tree Synthesis (CTS)
- Global and Detailed Routing (GRT/DRT)
- Parasitic Resistance/Capacitance Extraction (RCX)
- IR Drop Analysis
- Signoff
- Layout vs. Schematic (LVS)
- Checkers
- Misc.
- PDK Configuration Variables
- Tcl Commands
- Interactive Mode
- Datapoint Definitions
- Viewing layouts graphically
- Additional Material
- Authors
- Developer’s Guide